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2.5 v to 5.5 v, 120 a, 2-wire interface, voltage-output 8-/10-/12-bit dacs ad5301/ad5311/ad5321 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1999C2007 analog devices, inc. all rights reserved. features ad5301: buffered voltage output 8-bit dac ad5311: buffered voltage output 10-bit dac ad5321: buffered voltage output 12-bit dac 6-lead sot-23 and 8-lead msop packages micropower operation: 120 a @ 3 v 2-wire (i 2 c?-compatible) serial interface data readback capability 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 50 na @ 3 v reference derived from power supply power-on reset to 0 v on-chip rail-to-rail output buffer amplifier 3 power-down functions applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5301/ad5311/ad5321 1 are single 8-/10-/12-bit, buff- ered, voltage-output dacs that operate from a single 2.5 v to 5.5 v supply, consuming 120 a at 3 v. the on-chip output amplifier allows rail-to-rail output swing with a slew rate of 0.7 v/s. it uses a 2-wire (i 2 c-compatible) serial interface that operates at clock rates up to 400 khz. multiple devices can share the same bus. the reference for the dac is derived from the power supply inputs and thus gives the widest dynamic output range. these parts incorporate a power-on reset circuit, which ensures that the dac output powers up to 0 v and remains there until a valid write takes place. the parts contain a power-down feature that reduces the current consumption of the device to 50 na at 3 v and provides software-selectable output loads while in power-down mode. the low power consumption in normal operation makes these dacs ideally suited to portable battery-operated equipment. the power consumption is 0.75 mw at 5 v and 0.36 mw at 3 v, reducing to 1 w in all power-down modes. 1 protected by u.s. patent no. 5684481. functional block diagram resistor network buffer dac register power-down logic ad5301/ad5311/ad5321 v dd scl a0 gnd a1* ref power-on reset pd* sd a *available on 8-lead version only interface logic 8-/10-/12-bit dac v out 00927-001 figure 1.
ad5301/ad5311/ad5321 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac characteristics........................................................................ 5 timing characteristics ................................................................ 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 13 digital-to-analog ....................................................................... 13 resistor string ............................................................................. 13 output amplifier........................................................................ 13 power-on reset.......................................................................... 13 serial interface ................................................................................ 14 2-wire serial bus........................................................................ 14 input shift register .................................................................... 14 write operation.......................................................................... 15 read operation........................................................................... 16 power-down modes .................................................................. 17 application notes ........................................................................... 18 using ref19x as a power supply ............................................. 18 bipolar operation using the ad5301/ad5311/ad5321..... 18 multiple devices on one bus ................................................... 18 cmos driven scl and sda lines.......................................... 18 power supply decoupling ......................................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 revision history 3/07rev. a to rev. b updated format..................................................................universal changes to table 4............................................................................ 6 changes to figure 4 caption........................................................... 7 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 11/03rev. 0 to rev. a changes to ordering guide ............................................................ 4 updated outline dimensions ....................................................... 15 7/99revision 0: initial version
ad5301/ad5311/ad5321 rev. b | page 3 of 24 specifications v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. b version 1 parameter 2 min typ max unit conditions/comments dc performance 3 , 4 ad5301 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes. ad5311 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb gu aranteed monotonic by design over all codes. ad5321 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.3 0.8 lsb guaranteed monotonic by design over all codes. zero-code error 5 20 mv all zeros loaded to dac, see figure 12 . full-scale error 0.15 1.25 % of fsr all ones loaded to dac, see figure 12 . gain error 0.15 1 % of fsr zero-code error drift 5 C20 v/c gain error drift 5 ?5 ppm of fsr/c output characteristics 5 minimum output voltage 0.001 v maximum output voltage v dd ? 0.001 v this is a measure of the minimum and maximum drive capability of the output amplifier. dc output impedance 1 short-circuit current 50 ma v dd = 5 v. 20 ma v dd = 3 v. power-up time 2.5 s coming out of power-down mode. v dd = 5 v. 6 s coming out of power-down mode. v dd = 3 v. logic inputs (a0, a1, pd ) 5 input current 1 a input low voltage, v il 0.8 v v dd = 5 v 10%. 0.6 v v dd = 3 v 10%. 0.5 v v dd = 2.5 v. input high voltage, v ih 2.4 v v dd = 5 v 10%. 2.1 v v dd = 3 v 10%. 2.0 v v dd = 2.5 v. pin capacitance 3 pf logic inputs (scl, sda) 5 input high voltage, v ih 0.7 v dd v dd + 0.3 v input low voltage, v il ?0.3 +0.3 v dd v input leakage current, i in 1 a v in = 0 v to v dd . input hysteresis, v hyst 0.05 v dd v input capacitance, c in 6 pf glitch rejection 6 50 ns pulse width of spike suppressed.
ad5301/ad5311/ad5321 rev. b | page 4 of 24 b version 1 parameter 2 min typ max unit conditions/comments logic output (sda) 5 output low voltage, v ol 0.4 v i sink = 3 ma. 0.6 v i sink = 6 ma. three-state leakage current 1 a three-state output capacitance 6 pf power requirements v dd 2.5 5.5 v i dd specification is valid for all dac codes. i dd (normal mode) dac active and excluding load current. v dd = 4.5 v to 5.5 v 150 250 a v ih = v dd and v il = gnd. v dd = 2.5 v to 3.6 v 120 220 a v ih = v dd and v il = gnd. i dd (power-down mode) v dd = 4.5 v to 5.5 v 0.2 1 a v ih = v dd and v il = gnd. v dd = 2.5 v to 3.6 v 0.05 1 a v ih = v dd and v il = gnd. 1 temperature range is as follows: b versio n: ?40c to +105c. 2 see the terminology section. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5301 (code 7 to 250); ad5311 (code 28 to 1000); an d ad5321 (code 112 to 4000 ). 5 guaranteed by design and characterization, not production tested. 6 input filtering on both the scl and sda inputs suppress noise spikes that are less than 50 ns.
ad5301/ad5311/ad5321 rev. b | page 5 of 24 ac characteristics 1 v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. b version 2 parameter 3 min typ max unit conditions/comments output voltage settling time v dd = 5 v ad5301 6 8 s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5311 7 9 s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5321 8 10 s 1/4 scale to 3/ 4 scale change (0x400 to 0xc00) slew rate 0.7 v/s major-code change glitch impulse 12 nv-s 1 lsb change around major carry digital feedthrough 0.3 nv-s 1 see the terminology section. 2 temperature range for the b version is as follows: C40c to +105c. 3 guaranteed by design and characterization, not production tested. timing characteristics 1 v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. limit at t min , t max parameter 2 (b version) unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat, data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop co ndition and a start condition t 10 300 ns max t r , rise time of both scl and sda when receiving 4 0 ns min may be cmos driven t 11 250 ns max t f , fall time of sda when receiving 4 300 ns max t f , fall time of both scl and sda when transmitting 4 20 + 0.1c b 5 ns min c b 400 pf max capacitive load for each bus line 1 see figure 2. 2 guaranteed by design and characterization, not production tested. 3 a master device must provide a ho ld time of at least 300 ns for the sda signal (refer to the v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 4 t r and t f measured between 0.3 v dd and 0.7 v dd . 5 c b is the total capacitance of one bus line in picofarads. start condition repeated start condition stop condition sda scl t 9 t 3 t 10 t 4 t 6 t 5 t 2 t 11 t 7 t 4 t 1 t 8 00927-002 figure 2. 2-wire serial interface timing diagram
ad5301/ad5311/ad5321 rev. b | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. 1 table 4. parameter rating v dd to gnd ?0.3 v to +7 v scl, sda to gnd ?0.3 v to v dd + 0.3 v pd , a1, a0 to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c sot-23 package power dissipation (t j max ? t a )/ ja ja thermal impedance 229.6c/w msop package power dissipation (t j max C t a )/ ja ja thermal impedance 206c/w lead temperature jedec industry standard soldering j-std-020 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5301/ad5311/ad5321 rev. b | page 7 of 24 pin configurations and function descriptions a0 pd v out gnd v dd scl sda a1 ad5301/ ad5311/ ad5321 00927-004 1 2 3 4 8 7 6 5 top view (not to scale) gnd sda scl v dd a0 v out ad5301/ ad5311/ ad5321 0 0927-003 1 2 3 6 5 4 top view (not to scale) figure 3. 8-lead msop (rm-8) pin configuration figure 4. 6-lead sot-23 (rj-6) pin configuration table 5. pin function descriptions msop pin no. sot-23 pin no. mnemonic description 1 6 v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f in parallel with a 0.1 f capacitor to gnd. 2 5 a0 address input. sets the least si gnificant bit of the 7-bit slave address. 3 n/a a1 address input. sets the second le ast significant bit of the 7-bit slave address. 4 4 v out buffered analog output voltage from the dac. the output amplifier has rail-to-rail operation. 5 n/a pd active low control input. acts as a hardware power-down option. this pin overrides any software power-down option. the dac output goes three-stat e and the current consumption of the part drops to 50 na @ 3 v (200 na @ 5 v). 6 3 scl serial clock line. this is used in conjunction with the sda line to clock data into the 16-bit input shift register. clock rates of up to 400 kbps can be accommodated in the i 2 c-compatible interface. scl may be cmos/ttl driven. 7 2 sda serial data line. this is used in conjunction with the scl line to clock data into the 16-bit input shift register during the write cycle and to read back on e or two bytes of data (one byte for the ad5301, two bytes for the ad5311/ad5321) during the read cycle. it is a bidirectional open-drain data line that should be pulled to the supply with an external pu ll-up resistor. if not used in readback mode, sda may be cmos/ttl driven. 8 1 gnd ground reference point for all circuitry on the part.
ad5301/ad5311/ad5321 rev. b | page 8 of 24 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the actual endpoints of the dac transfer function. typical inl vs. code plots can be seen in figure 5 to figure 7 . differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonic- ity. these dacs are guaranteed monotonic by design over all codes. typical dnl vs. code plots can be seen in figure 8 to figure 10 . zero-code error zero-code error is a measure of the output error when zero code (0x00) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error of the ad5301/ad5311/ ad5321 is always positive because the output of the dac cannot go below 0 v, due to a combination of the offset errors in the dac and output amplifier. it is expressed in millivolts, see figure 12 . full-scale error (fsr) full-scale error is a measure of the output error when full scale is loaded to the dac register. ideally, the output should be v dd C 1 lsb. full-scale error is expressed in percent of fsr. a plot can be seen in figure 12 . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. major code transition glitch energy major code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device, but is measured when the dac is not being written to. it is specified in nv-s and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa.
ad5301/ad5311/ad5321 rev. b | page 9 of 24 typical performance characteristics 1.0 0.5 0 ?0.5 ?1.0 0 50 100 150 200 255 inl error (lsb) code t a = 25c v dd = 5v 0 0927-005 figure 5. ad5301 typical inl plot 3 1 0 ?2 ?3 0 200 400 600 800 1023 inl error (lsb) code t a = 25c v dd = 5v ?1 2 7-00 3 1 0 ?8 ?12 0 1000 2000 3000 4095 inl error (lsb) code ?4 2 0092 6 figure 6. ad5311 typical inl plot t a = 25c v dd = 5v 00927-007 figure 7. ad5321 typical inl plot 0.3 0.1 0 ?0.2 ?0.3 0 50 100 150 255 dnl error (lsb) code ?0.1 0.2 200 7-00 t a = 25c v dd = 5v 0092 8 figure 8. ad5301 typical dnl plot 0.6 0.2 0 ?0.4 ?0.6 0 200 400 600 800 1023 dnl error (lsb) code ?0.2 0.4 t a = 25c v dd = 5v 0092 9 7-00 1.0 0.5 0 ?0.5 ?1.0 0 1000 2000 3000 4095 dnl error (lsb) code figure 9. ad5311 typical dnl plot t a = 25c v dd = 5v 00927-010 figure 10. ad5321 typical dnl plot
ad5301/ad5311/ad5321 rev. b | page 10 of 24 v dd = 5v max inl 1.00 0.75 0.50 0 ?0.50 0.25 ?0.25 ?0.75 ?1.00 ?40 0 40 80 120 error (lsb) temperature (c) max dnl min inl min dnl 00927-011 figure 11. ad5301 inl error and dnl error vs. temperature 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?40 0 40 80 60 20 ?20 100 error (mv) temperature (c) zero code full scale v dd = 5v 0 0927-012 figure 12. zero-code error and full-scale error vs. temperature 80 120 160 190 140 100 200 frequency (hz) i dd (a) v dd = 5v v dd = 3v 00927-013 figure 13. i dd histogram with v dd = 3 v and v dd = 5 v 4 1 ?0 03691 21 v out (v) i (ma) 2 3 5 5 5v sink 3v sink 5v source 3v source 0 0927-014 figure 14. source and si nk current capability i dd (a) code 200 zero scale full scale 180 160 140 120 100 80 60 40 20 0 v dd = 5v t a = 25c v dd = 5v v dd = 3v 0 0927-015 figure 15. supply current vs. code i dd (a) v dd (v) 200 2.7 3.2 3.7 4.2 4.7 5.2 150 100 50 0 +25c ?40c +105c 00927-016 figure 16. supply current vs. supply voltage
ad5301/ad5311/ad5321 rev. b | page 11 of 24 i dd (a) v dd (v) 1.0 2.7 3.2 3.7 4.2 4.7 5.2 0.8 0.6 0.4 0.2 0 +25c ?40c +105c 00927-017 figure 17. power-down current vs. supply voltage i dd (a) v logic (v) 300 0 1.0 2.0 3.0 4.0 5.0 250 200 150 100 50 0 decreasing t a = 25c v dd = 5v v dd = 3v increasing 00927-018 figure 18. supply current vs. logic input voltage for sda and scl voltage increasing and decreasing ch1 1v, time base = 5s/div 1 v dd = 5v t a = 25c load = 2k ? and 200pf to gnd v out 00927-019 figure 19. half-scale settling (1/4 to 3/4 scale code charge) ch2 ch1 1v, ch2 1v, time base = 20s/div ch1 v out t a = 25c v dd 00927-020 figure 20. power-on reset to 0 v
ad5301/ad5311/ad5321 rev. b | page 12 of 24 c h2 ch1 1v, ch2 5v, time base = 1s/div c h1 t a = 25c v dd = 5v v out clk 00927-021 figure 21. exiting po wer-down to midscale 2.48 2.47 v out (v) 2.49 2.50 1s/div 00927-022 figure 22. major-code transition 2.440 2.445 2.450 2.455 v out (v) 1ns/div 00927-023 figure 23. digital feedthrough
ad5301/ad5311/ad5321 rev. b | page 13 of 24 theory of operation the ad5301/ad5311/ad5321 are single resistor-string dacs fabricated on a cmos process with resolutions of 8/10/12 bits, respectively. data is written via a 2-wire serial interface. the devices operate from single supplies of 2.5 v to 5.5 v and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/s. the power supply (v dd ) acts as the reference to the dac. the ad5301/ad5311/ad5321 have three programmable power-down modes, in which the dac can be turned off completely with a high impedance output, or the output can be pulled low by an on-chip resistor (see the power-down modes section). digital-to-analog the architecture of the dac channel consists of a resistor string dac followed by an output buffer amplifier. the voltage at the v dd pin provides the reference voltage for the dac. figure 24 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by n dd out dv v 2 = where: n = dac resolution d = decimal equivalent of the binary code that is loaded to the dac register: 0C255 for ad5301 (8 bits) 0C1023 for ad5311 (10 bits) 0C4095 for ad5321 (12 bits) dac register resistor string output buffer amplifier ref(+) ref(?) gnd v dd v out 00927-024 figure 24. dac channel architecture resistor string the resistor string section is shown in figure 25 . it is simply a string of resistors, each with a value of r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output ampli- fier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic over all codes. r r r r r to output amplifier 00927-025 figure 25. resistor string output amplifier the output buffer amplifier is capable of generating output volt- ages to within 1 mv from either rail, which gives an output range of 0.001 v to v dd ? 0.001 v. it is capable of driving a load of 2 k to gnd and v dd , in parallel with 500 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 14 . the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at 8 bits) of 6 s with the output unloaded. power-on reset the ad5301/ad5311/ad5321 are provided with a power-on reset function, ensuring that they power up in a defined state. the dac register is filled with zeros and remains so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac output while the device is powering up.
ad5301/ad5311/ad5321 rev. b | page 14 of 24 serial interface 2-wire serial bus the ad5301/ad5311/ad5321 are controlled via an i 2 c- compatible serial bus. the dacs are connected to this bus as slave devices (no clock is generated by the ad5301/ad5311/ ad5321 dacs). the ad5301/ad5311/ad5321 has a 7-bit slave address. in the case of the 6-lead device, the six msbs are 000110 and the lsb is determined by the state of the a0 pin. in the case of the 8-lead device, the five msbs are 00011 and the two lsbs are determined by the state of the a0 and a1 pins. a1 and a0 allow the user to use up to four of these dacs on one bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte that consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. however, if the r/ w bit is low, the master writes to the slave device. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop con- dition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condi- tion. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse and then high during the 10 th clock pulse to establish a stop condition. in the case of the ad5301/ad5311/ad5321, a write operation contains two bytes whereas a read operation may contain one or two bytes. see figure 29 to figure 34 for a graphical explanation of the serial interface. a repeated write function gives the user flexibility to update the dac output a number of times after addressing the part only once. during the write cycle, each multiple of two data bytes updates the dac output. for example, after the dac acknowl- edges its address byte, and receives two data bytes; the dac output updates after the two data bytes, if another two data bytes are written to the dac while it is still the addressed slave device. these data bytes also cause an output update. a repeat read of the dac is also allowed. input shift register the input shift register is 16 bits wide. figure 26, figure 27, and figure 28 illustrate the contents of the input shift register for each part. data is loaded into the device as a 16-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 2. the 16-bit word consists of four control bits followed by 8/10/12 bits of data, depending on the device type. msb (bit 15) is loaded first. the first two bits are dont cares. the next two are control bits that control the mode of operation of the device (normal mode or any one of three power-down modes). see the power-down modes section for a complete description. the remaining bits are left justified dac data bits, starting with the msb and ending with the lsb. xx xxxx db0 (lsb) db15 (msb) data bits pd1 pd0 d7 d6 d5 d4 d3 d2 d1 d0 0 0927-026 figure 26. ad5301 input shift register contents db0 (lsb) db15 (msb) d7 d8 d6 d5 x x d1 d0 x x pd1 pd0 d9 d4 d3 d2 data bits 0 0927-037 figure 27. ad5311 input shift register contents data bits db0 (lsb) db15 (msb) x x pd1 pd0 d11 d10 d9 d8 d7 d6 d4 d5 d3 d2 d1 d0 00927-038 figure 28. ad5321 input shift register contents
ad5301/ad5311/ad5321 rev. b | page 15 of 24 write operation when writing to the ad5301/ad5311/ad5321 dacs, the user must begin with an address byte, after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is followed by the 16-bit word in the form of two control bytes. the write operations for the three dacs are shown in figure 29 to figure 31 . scl s d a scl s d a least significant control byte ack by ad5301 ack by ad5301 start cond by master *this bit must be 0 in the 6-lead sot-23 version. ack by ad5301 stop cond by master pd1 x x pd0 d7 d6 d5 d4 most significant control byte address byte 0a 1 * a 0 0011 r/w d3 d2 d1 d0 x x x x 0 0927-027 figure 29. ad5301 write sequence scl sd a scl sd a least significant control byte ack by ad5311 ack by ad5311 start cond by master *this bit must be 0 in the 6-lead sot-23 version. ack by ad5311 stop cond by master pd1 x x pd0 d9 d8 d7 d6 most significant control byte address byte 0a 1 * a 0 0011 r/w d5 d4 d3 d2 d1 d0 x x 00927-028 figure 30. ad5311 write sequence scl sda scl sda least significant control byte ack by ad5321 ack by ad5321 start cond by master *this bit must be 0 in the 6-lead sot-23 version. ack by ad5321 stop cond by master pd1 x x pd0 d11 d10 d9 d8 most significant control byte address byte 0a 1 * a 0 0011 r/w d7 d6 d5 d4 d3 d2 d1 d0 00927-029 figure 31. ad5321 write sequence
ad5301/ad5311/ad5321 rev. b | page 16 of 24 read operation when reading data back from the ad5301/ad5311/ad5321 dacs, the user must begin with an address byte after which the dac acknowledges that it is prepared to transmit data by pulling sda low. there are two different read operations. in the case of the ad5301, the readback is a single byte that consists of the eight data bits in the dac register. however, in the case of the ad5311 and ad5321, the readback consists of two bytes that contain both the data and the power-down mode bits. the read operations for the three dacs are shown in figure 32 to figure 34 . scl sda ack by ad5301 no ack by master start cond by master *this bit must be 0 in the 6-lead sot-23 version. address byte 00011 a1* a0 r/w stop cond by master data byte d7 d6 d5 d4 d3 d2 d1 d0 00927-030 figure 32. ad5301 readback sequence scl sda scl sda least significant control byte *this bit must be 0 in the 6-lead sot-23 version. no ack by master stop cond by master pd1 x x pd0 d9 d8 d7 d6 0a 1 * a 0 0011 r/w d5 d4 d3 d2 d1 d0 x x ack by ad5311 ack by ad5311 start cond by master most significant byte address byte 00927-031 figure 33. ad5311 readback sequence least significant byte scl sd a scl sd a ack by ad5321 no ack by master start cond by master stop cond by master *this bit must be 0 in the 6-lead sot-23 version. address byte stop cond by master most siignificant byte 0 d7 d6 d5 d4 d3 d2 d1 d0 0011 a1* a0 r/w x x pd1 pd0 d11 d10 d9 d8 00927-032 figure 34. ad5321 readback sequence
ad5301/ad5311/ad5321 rev. b | page 17 of 24 power-down modes the ad5301/ad5311/ad5321 have very low power consump- tion, dissipating typically 0.36 mw with a 3 v supply and 0.75 mw with a 5 v supply. power consumption can be further reduced when the dac is not in use by putting it into one of three power-down modes, which are selected by bit 13 and bit 12 (pd1 and pd0) of the control word. table 6 shows how the state of the bits corresponds to the mode of operation of the dac. table 6. pd1 and pd0 operating modes pd1 pd0 operating mode 0 0 normal operation 0 1 power-down (1 k load to gnd) 1 0 power-down (100 k load to gnd) 1 1 power-down (three-state output) the software power-down modes programmed by pd1 and pd0 may be overridden by the pd pin on the 8-lead version. taking this pin low puts the dac into three-state power-down mode. if pd is not used, tie it high. when both bits are set to 0, the dac works normally with its normal power consumption of 150 a at 5 v, while for the three power-down modes, the supply current falls to 200 na at 5 v (50 na at 3 v). not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. there are three different options. the output is con- nected internally to gnd through a 1 k resistor, a 100 k resistor, or it is left three-stated. resistor tolerance = 20%. the output stage is illustrated in figure 35 . register string dac amplifier v out power-down circuitry resistor network 00927-033 figure 35. output stage during power-down the bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the dac register are unchanged when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 6 s when v dd = 3 v (see figure 21 ).
ad5301/ad5311/ad5321 rev. b | page 18 of 24 applications notes using ref19x as a power supply because the supply current required by the ad5301/ad5311/ ad5321 is extremely low, the user has an alternative option to employ a ref195 voltage reference (for 5 v) or a ref193 voltage reference (for 3 v) to supply the required voltage to the part (see figure 36 ). sda scl 5v 150a typ ref195 2-wire serial interface v dd ad5301/ ad5311/ ad5321 v out = 0v to 5v 00927-034 figure 36. ref195 as power supply to ad5301/ad5311/ad5321 this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v (for example, 15 v). the ref193 / ref195 output a steady supply voltage for the ad5301/ad5311/ad5321. if the low dropout ref195 is used, it needs to supply a current of 150 a to the ad5301/ad5311/ad5321. this is with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 2 k load on the dac output and full scale loaded to the dac) is 150 a + (5 v/2 k) = 2.65 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.3 ppm (26.5 v) for the 2.65 ma current drawn from it. this corresponds to a 0.00136 lsb error. bipolar operation using the ad5301/ ad5311/ad5321 the ad5301/ad5311/ad5321 has been designed for single- supply operation, but a bipolar output range is also possible using the circuit in figure 37 . the circuit below gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. ad5301/ ad5311/ ad5321 2-wire serial interface v out v dd 10f 0.1f +5v +5v ?5v r2 10k ? ad820/ op295 r1 10k ? 5v 00927-035 figure 37. bipolar operation with the ad5301/ad5311/ad5321 the output voltage for any input code can be calculated as v out = [( v dd ( d /2 n ) r1 + r2 )/ r1 ) ? v dd ( r2 / r1 )] where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. with v dd = 5 v, r1 = r2 = 10 k, v out = (10 d /2 n ) ? 5 v multiple devices on one bus figure 38 shows four ad5301 devices on the same serial bus. each has a different slave address since the state of their a0 and a1 pins is different. this allows each dac to be written to or read from independently. the master device output bus line drivers are open-drain, pull-downs in a fully i 2 c-compatible interface. cmos driven scl and sda lines for single or multisupply systems where the minimum scl swing requirements allow it, a cmos scl driver may be used, and the scl pull-up resistor can be removed, making the scl bus line fully cmos compatible. this reduces power consump- tion in both the scl driver and receiver devices. the sda line remains open-drain, i 2 c compatible. further changes, in the sda line driver, may be made to make the system more cmos compatible and save more power. as the sda line is bidirectional, it cannot be made fully cmos compatible. a switched pull-up resistor can be combined with a cmos device with an open-circuit (three-state) input such that the cmos sda driver is enabled during write cycles and i 2 c mode is enabled during shared cycles, that is, readback, acknowledge bit cycles, start conditions, and stop conditions.
ad5301/ad5311/ad5321 rev. b | page 19 of 24 power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the ad5301/ad5311/ad5321 should be decoupled to gnd with 10 f in parallel with a 0.1 f capacitor, located as close to the package as possible. the 10 f capacitor should be the tantalum bead type, while a ceramic 0.1 f capacitor provides a sufficient low impedance path to ground at high frequencies. the power supply lines of the ad5301/ad5311/ad5321 should use as large a trace as possible to provide low impedance paths. a ground line routed between the sda and scl lines helps reduce crosstalk between them. this is not required on a multilayer board as there is a ground plane layer, but separating the lines helps. ad5301 a1 a0 v out ad5301 a1 a0 ad5301 a1 a0 ad5301 a1 a0 scl scl sda sda scl sda scl sda scl sda 5 v master r p r p v out v out v out v dd v dd v dd 00927-036 figure 38. multiple ad5301 devices on one bus
ad5301/ad5311/ad5321 rev. b | page 20 of 24 outline dimensions 1 3 4 5 2 6 2.90 bsc 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.60 0.45 0.30 pin 1 indicator compliant to jedec standards mo-178-ab figure 39. 6-lead small outline transistor package [sot-23] (rj-6) dimensions shown in millimeters compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 40. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad5301/ad5311/ad5321 rev. b | page 21 of 24 ordering guide model temperature range package description package option branding ad5301brm C40c to +105c 8-lead msop rm-8 d8b ad5301brm-reel C40c to +105c 8-lead msop rm-8 d8b ad5301brm-reel7 C40c to +105c 8-lead msop rm-8 d8b ad5301brmz 1 C40c to +105c 8-lead msop rm-8 d8b# ad5301brmz-reel 1 C40c to +105c 8-lead msop rm-8 d8b# ad5301brmz-reel7 1 C40c to +105c 8-lead msop rm-8 d8b# ad5301brt-500rl7 C40c to +105c 6-lead sot-23 rj-6 d8b ad5301brt-reel C40c to +105c 6-lead sot-23 rj-6 d8b ad5301brt-reel7 C40c to +105c 6-lead sot-23 rj-6 d8b ad5301brtz-500rl7 1 C40c to +105c 6-lead sot-23 rj-6 d8b# AD5301BRTZ-REEL 1 C40c to +105c 6-lead sot-23 rj-6 d8b# AD5301BRTZ-REEL7 1 C40c to +105c 6-lead sot-23 rj-6 d8b# ad5311brm C40c to +105c 8-lead msop rm-8 d9b ad5311brm-reel C40c to +105c 8-lead msop rm-8 d9b ad5311brm-reel7 C40c to +105c 8-lead msop rm-8 d9b ad5311brmz 1 C40c to +105c 8-lead msop rm-8 d9b# ad5311brmz-reel 1 C40c to +105c 8-lead msop rm-8 d9b# ad5311brmz-reel7 1 C40c to +105c 8-lead msop rm-8 d9b# ad5311brt-500rl7 C40c to +105c 6-lead sot-23 rj-6 d9b ad5311brt-reel C40c to +105c 6-lead sot-23 rj-6 d9b ad5311brt-reel7 C40c to +105c 6-lead sot-23 rj-6 d9b ad5311brtz-500rl7 1 C40c to +105c 6-lead sot-23 rj-6 d9b# ad5311brtz-reel 1 C40c to +105c 6-lead sot-23 rj-6 d9b# ad5311brtz-reel7 1 C40c to +105c 6-lead sot-23 rj-6 d9b# ad5321brm C40c to +105c 8-lead msop rm-8 dab ad5321brm-reel C40c to +105c 8-lead msop rm-8 dab ad5321brm-reel7 C40c to +105c 8-lead msop rm-8 dab ad5321brmz 1 C40c to +105c 8-lead msop rm-8 dab# ad5321brmz-reel 1 C40c to +105c 8-lead msop rm-8 dab# ad5321brmz-reel7 1 C40c to +105c 8-lead msop rm-8 dab# ad5321brt-500rl7 C40c to +105c 6-lead sot-23 rj-6 dab ad5321brt-reel C40c to +105c 6-lead sot-23 rj-6 dab ad5321brt-reel7 C40c to +105c 6-lead sot-23 rj-6 dab ad5321brtz-500rl7 1 C40c to +105c 6-lead sot-23 rj-6 dab# ad5321brtz-reel 1 C40c to +105c 6-lead sot-23 rj-6 dab# ad5321brtz-reel7 1 C40c to +105c 6-lead sot-23 rj-6 dab# 1 z = rohs compliant part; # denotes rohs compliant product, may be top or bottom marked.
ad5301/ad5311/ad5321 rev. b | page 22 of 24 notes
ad5301/ad5311/ad5321 rev. b | page 23 of 24 notes
ad5301/ad5311/ad5321 rev. b | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?1999C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00927-0-3/07(b)

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